(1) Field of the Invention
This invention relates to read only memory (ROM) type semiconductor devices and in particular, to an improved process for forming high density self-aligned conductive lines on a semiconductor substrate.
(2) Description of the Prior Art
In the quest to achieve microminiaturization of integrated circuit devices, individual elements have been made very small and the elements have been closely packed. Furthermore, as read only memory devices (ROM's) are scaled down in dimension, there is a continuous challenge to produce high density closely packed conductive lines using a minimum number of process steps. In producing read only memory devices, the maximum packing, or the minimum feature size, is determined by the photolithographic capability. Moreover, in the conventional prior art process for producing ROM's, the photolithographic capability is a limiting factor for determining the minimum conductive line width, pitch, and spacing.
In the conventional prior art process for ROM fabrication, shown in cross-sectional FIGS. 1 and 2, an insulating layer 12, typically oxide, is deposited on a monocrystalline silicon substrate 10. Subsequently, a blanket conductive layer 14, formed of doped polycrystalline silicon or a polycide layer, is deposited over the insulating layer 12. Next, photoresist layer 16 is deposited over the blanket conductive layer 14. The photoresist layer 16 is exposed and developed to form elongated openings 18 that define the spaces between the conductive lines. Next, referring to FIG. 2, the exposed conductive layer 14 is etched away to form the word lines 20. Subsequently, an insulating layer (not shown) is deposited in the space between the word lines. The process steps to complete the read only memory device (ROM) device are well known.